YES(?,POLY) * Step 1: TrivialSCCs WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedpldi4_start(v_i_0,v_m,v_n) -> eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) True (1,1) 1. eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) -> eval_speedpldi4_0(v_i_0,v_m,v_n) True (?,1) 2. eval_speedpldi4_0(v_i_0,v_m,v_n) -> eval_speedpldi4_1(v_i_0,v_m,v_n) True (?,1) 3. eval_speedpldi4_1(v_i_0,v_m,v_n) -> eval_speedpldi4_2(v_i_0,v_m,v_n) True (?,1) 4. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [0 >= v_m] (?,1) 5. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [v_m >= v_n] (?,1) 6. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_n,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (?,1) 7. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -1 + v_i_0 >= 0] 8. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && 0 >= v_i_0] 9. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(-1 + v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && -1 + v_m >= v_i_0] 10. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_i_0 + -1*v_m,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && v_i_0 >= v_m] 11. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> eval_speedpldi4_stop(v_i_0,v_m,v_n) True (?,1) Signature: {(eval_speedpldi4_0,3) ;(eval_speedpldi4_1,3) ;(eval_speedpldi4_2,3) ;(eval_speedpldi4_bb0_in,3) ;(eval_speedpldi4_bb1_in,3) ;(eval_speedpldi4_bb2_in,3) ;(eval_speedpldi4_bb3_in,3) ;(eval_speedpldi4_start,3) ;(eval_speedpldi4_stop,3)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{11},5->{11},6->{7,8},7->{9,10},8->{11},9->{7,8},10->{7,8},11->{}] + Applied Processor: TrivialSCCs + Details: All trivial SCCs of the transition graph admit timebound 1. * Step 2: UnsatPaths WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedpldi4_start(v_i_0,v_m,v_n) -> eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) True (1,1) 1. eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) -> eval_speedpldi4_0(v_i_0,v_m,v_n) True (1,1) 2. eval_speedpldi4_0(v_i_0,v_m,v_n) -> eval_speedpldi4_1(v_i_0,v_m,v_n) True (1,1) 3. eval_speedpldi4_1(v_i_0,v_m,v_n) -> eval_speedpldi4_2(v_i_0,v_m,v_n) True (1,1) 4. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [0 >= v_m] (1,1) 5. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [v_m >= v_n] (1,1) 6. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_n,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (1,1) 7. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -1 + v_i_0 >= 0] 8. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (1,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && 0 >= v_i_0] 9. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(-1 + v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && -1 + v_m >= v_i_0] 10. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_i_0 + -1*v_m,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && v_i_0 >= v_m] 11. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> eval_speedpldi4_stop(v_i_0,v_m,v_n) True (1,1) Signature: {(eval_speedpldi4_0,3) ;(eval_speedpldi4_1,3) ;(eval_speedpldi4_2,3) ;(eval_speedpldi4_bb0_in,3) ;(eval_speedpldi4_bb1_in,3) ;(eval_speedpldi4_bb2_in,3) ;(eval_speedpldi4_bb3_in,3) ;(eval_speedpldi4_start,3) ;(eval_speedpldi4_stop,3)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{11},5->{11},6->{7,8},7->{9,10},8->{11},9->{7,8},10->{7,8},11->{}] + Applied Processor: UnsatPaths + Details: We remove following edges from the transition graph: [(6,8)] * Step 3: AddSinks WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedpldi4_start(v_i_0,v_m,v_n) -> eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) True (1,1) 1. eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) -> eval_speedpldi4_0(v_i_0,v_m,v_n) True (1,1) 2. eval_speedpldi4_0(v_i_0,v_m,v_n) -> eval_speedpldi4_1(v_i_0,v_m,v_n) True (1,1) 3. eval_speedpldi4_1(v_i_0,v_m,v_n) -> eval_speedpldi4_2(v_i_0,v_m,v_n) True (1,1) 4. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [0 >= v_m] (1,1) 5. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [v_m >= v_n] (1,1) 6. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_n,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (1,1) 7. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -1 + v_i_0 >= 0] 8. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (1,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && 0 >= v_i_0] 9. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(-1 + v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && -1 + v_m >= v_i_0] 10. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_i_0 + -1*v_m,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && v_i_0 >= v_m] 11. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> eval_speedpldi4_stop(v_i_0,v_m,v_n) True (1,1) Signature: {(eval_speedpldi4_0,3) ;(eval_speedpldi4_1,3) ;(eval_speedpldi4_2,3) ;(eval_speedpldi4_bb0_in,3) ;(eval_speedpldi4_bb1_in,3) ;(eval_speedpldi4_bb2_in,3) ;(eval_speedpldi4_bb3_in,3) ;(eval_speedpldi4_start,3) ;(eval_speedpldi4_stop,3)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{11},5->{11},6->{7},7->{9,10},8->{11},9->{7,8},10->{7,8},11->{}] + Applied Processor: AddSinks + Details: () * Step 4: UnsatPaths WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedpldi4_start(v_i_0,v_m,v_n) -> eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) True (1,1) 1. eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) -> eval_speedpldi4_0(v_i_0,v_m,v_n) True (?,1) 2. eval_speedpldi4_0(v_i_0,v_m,v_n) -> eval_speedpldi4_1(v_i_0,v_m,v_n) True (?,1) 3. eval_speedpldi4_1(v_i_0,v_m,v_n) -> eval_speedpldi4_2(v_i_0,v_m,v_n) True (?,1) 4. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [0 >= v_m] (?,1) 5. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [v_m >= v_n] (?,1) 6. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_n,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (?,1) 7. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -1 + v_i_0 >= 0] 8. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && 0 >= v_i_0] 9. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(-1 + v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && -1 + v_m >= v_i_0] 10. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_i_0 + -1*v_m,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && v_i_0 >= v_m] 11. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> eval_speedpldi4_stop(v_i_0,v_m,v_n) True (?,1) 12. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> exitus616(v_i_0,v_m,v_n) True (?,1) Signature: {(eval_speedpldi4_0,3) ;(eval_speedpldi4_1,3) ;(eval_speedpldi4_2,3) ;(eval_speedpldi4_bb0_in,3) ;(eval_speedpldi4_bb1_in,3) ;(eval_speedpldi4_bb2_in,3) ;(eval_speedpldi4_bb3_in,3) ;(eval_speedpldi4_start,3) ;(eval_speedpldi4_stop,3) ;(exitus616,3)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{11,12},5->{11,12},6->{7,8},7->{9,10},8->{11,12},9->{7,8},10->{7,8} ,11->{},12->{}] + Applied Processor: UnsatPaths + Details: We remove following edges from the transition graph: [(6,8)] * Step 5: LooptreeTransformer WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedpldi4_start(v_i_0,v_m,v_n) -> eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) True (1,1) 1. eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) -> eval_speedpldi4_0(v_i_0,v_m,v_n) True (?,1) 2. eval_speedpldi4_0(v_i_0,v_m,v_n) -> eval_speedpldi4_1(v_i_0,v_m,v_n) True (?,1) 3. eval_speedpldi4_1(v_i_0,v_m,v_n) -> eval_speedpldi4_2(v_i_0,v_m,v_n) True (?,1) 4. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [0 >= v_m] (?,1) 5. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [v_m >= v_n] (?,1) 6. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_n,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (?,1) 7. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -1 + v_i_0 >= 0] 8. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && 0 >= v_i_0] 9. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(-1 + v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && -1 + v_m >= v_i_0] 10. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_i_0 + -1*v_m,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && v_i_0 >= v_m] 11. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> eval_speedpldi4_stop(v_i_0,v_m,v_n) True (?,1) 12. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> exitus616(v_i_0,v_m,v_n) True (?,1) Signature: {(eval_speedpldi4_0,3) ;(eval_speedpldi4_1,3) ;(eval_speedpldi4_2,3) ;(eval_speedpldi4_bb0_in,3) ;(eval_speedpldi4_bb1_in,3) ;(eval_speedpldi4_bb2_in,3) ;(eval_speedpldi4_bb3_in,3) ;(eval_speedpldi4_start,3) ;(eval_speedpldi4_stop,3) ;(exitus616,3)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{11,12},5->{11,12},6->{7},7->{9,10},8->{11,12},9->{7,8},10->{7,8} ,11->{},12->{}] + Applied Processor: LooptreeTransformer + Details: We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,12] | `- p:[7,9,10] c: [10] | `- p:[7,9] c: [9] * Step 6: SizeAbstraction WORST_CASE(?,POLY) + Considered Problem: (Rules: 0. eval_speedpldi4_start(v_i_0,v_m,v_n) -> eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) True (1,1) 1. eval_speedpldi4_bb0_in(v_i_0,v_m,v_n) -> eval_speedpldi4_0(v_i_0,v_m,v_n) True (?,1) 2. eval_speedpldi4_0(v_i_0,v_m,v_n) -> eval_speedpldi4_1(v_i_0,v_m,v_n) True (?,1) 3. eval_speedpldi4_1(v_i_0,v_m,v_n) -> eval_speedpldi4_2(v_i_0,v_m,v_n) True (?,1) 4. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [0 >= v_m] (?,1) 5. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [v_m >= v_n] (?,1) 6. eval_speedpldi4_2(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_n,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (?,1) 7. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -1 + v_i_0 >= 0] 8. eval_speedpldi4_bb1_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && 0 >= v_i_0] 9. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(-1 + v_i_0,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && -1 + v_m >= v_i_0] 10. eval_speedpldi4_bb2_in(v_i_0,v_m,v_n) -> eval_speedpldi4_bb1_in(v_i_0 + -1*v_m,v_m,v_n) [-2 + v_n >= 0 (?,1) && -3 + v_m + v_n >= 0 && -1 + -1*v_m + v_n >= 0 && -3 + v_i_0 + v_n >= 0 && -1*v_i_0 + v_n >= 0 && -1 + v_m >= 0 && -2 + v_i_0 + v_m >= 0 && -1 + v_i_0 >= 0 && v_i_0 >= v_m] 11. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> eval_speedpldi4_stop(v_i_0,v_m,v_n) True (?,1) 12. eval_speedpldi4_bb3_in(v_i_0,v_m,v_n) -> exitus616(v_i_0,v_m,v_n) True (?,1) Signature: {(eval_speedpldi4_0,3) ;(eval_speedpldi4_1,3) ;(eval_speedpldi4_2,3) ;(eval_speedpldi4_bb0_in,3) ;(eval_speedpldi4_bb1_in,3) ;(eval_speedpldi4_bb2_in,3) ;(eval_speedpldi4_bb3_in,3) ;(eval_speedpldi4_start,3) ;(eval_speedpldi4_stop,3) ;(exitus616,3)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{11,12},5->{11,12},6->{7},7->{9,10},8->{11,12},9->{7,8},10->{7,8} ,11->{},12->{}] ,We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,12] | `- p:[7,9,10] c: [10] | `- p:[7,9] c: [9]) + Applied Processor: SizeAbstraction UseCFG Minimize + Details: () * Step 7: FlowAbstraction WORST_CASE(?,POLY) + Considered Problem: Program: Domain: [v_i_0,v_m,v_n,0.0,0.0.0] eval_speedpldi4_start ~> eval_speedpldi4_bb0_in [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb0_in ~> eval_speedpldi4_0 [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_0 ~> eval_speedpldi4_1 [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_1 ~> eval_speedpldi4_2 [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_2 ~> eval_speedpldi4_bb3_in [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_2 ~> eval_speedpldi4_bb3_in [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_2 ~> eval_speedpldi4_bb1_in [v_i_0 <= v_n, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb2_in [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb3_in [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_i_0 <= v_n, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_i_0 <= v_n, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb3_in ~> eval_speedpldi4_stop [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb3_in ~> exitus616 [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] + Loop: [0.0 <= v_i_0] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb2_in [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_i_0 <= v_n, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_i_0 <= v_n, v_m <= v_m, v_n <= v_n] + Loop: [0.0.0 <= v_i_0] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb2_in [v_i_0 <= v_i_0, v_m <= v_m, v_n <= v_n] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_i_0 <= v_n, v_m <= v_m, v_n <= v_n] + Applied Processor: FlowAbstraction + Details: () * Step 8: LareProcessor WORST_CASE(?,POLY) + Considered Problem: Program: Domain: [tick,huge,K,v_i_0,v_m,v_n,0.0,0.0.0] eval_speedpldi4_start ~> eval_speedpldi4_bb0_in [] eval_speedpldi4_bb0_in ~> eval_speedpldi4_0 [] eval_speedpldi4_0 ~> eval_speedpldi4_1 [] eval_speedpldi4_1 ~> eval_speedpldi4_2 [] eval_speedpldi4_2 ~> eval_speedpldi4_bb3_in [] eval_speedpldi4_2 ~> eval_speedpldi4_bb3_in [] eval_speedpldi4_2 ~> eval_speedpldi4_bb1_in [v_n ~=> v_i_0] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb2_in [] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb3_in [] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_n ~=> v_i_0] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_n ~=> v_i_0] eval_speedpldi4_bb3_in ~> eval_speedpldi4_stop [] eval_speedpldi4_bb3_in ~> exitus616 [] + Loop: [v_i_0 ~=> 0.0] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb2_in [] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_n ~=> v_i_0] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_n ~=> v_i_0] + Loop: [v_i_0 ~=> 0.0.0] eval_speedpldi4_bb1_in ~> eval_speedpldi4_bb2_in [] eval_speedpldi4_bb2_in ~> eval_speedpldi4_bb1_in [v_n ~=> v_i_0] + Applied Processor: LareProcessor + Details: eval_speedpldi4_start ~> eval_speedpldi4_stop [v_n ~=> v_i_0 ,v_n ~=> 0.0 ,v_n ~=> 0.0.0 ,v_n ~+> tick ,tick ~+> tick ,v_n ~*> tick] eval_speedpldi4_start ~> exitus616 [v_n ~=> v_i_0 ,v_n ~=> 0.0 ,v_n ~=> 0.0.0 ,v_n ~+> tick ,tick ~+> tick ,v_n ~*> tick] + eval_speedpldi4_bb1_in> [v_i_0 ~=> 0.0 ,v_i_0 ~=> 0.0.0 ,v_n ~=> v_i_0 ,v_n ~=> 0.0.0 ,v_i_0 ~+> tick ,v_n ~+> tick ,tick ~+> tick ,v_i_0 ~*> tick] + eval_speedpldi4_bb1_in> [v_i_0 ~=> 0.0.0 ,v_n ~=> v_i_0 ,v_i_0 ~+> tick ,tick ~+> tick] YES(?,POLY)