MAYBE * Step 1: TrivialSCCs MAYBE + Considered Problem: Rules: 0. eval_speedpldi3_start(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) True (1,1) 1. eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) True (?,1) 2. eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) True (?,1) 3. eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) True (?,1) 4. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [0 >= v_m] (?,1) 5. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_m >= v_n] (?,1) 6. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(0,0,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (?,1) 7. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) [-1 + v_n >= v_i_0] (?,1) 8. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_i_0 >= v_n] (?,1) 9. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && -1 + v_m >= v_j_0] (?,1) 10. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && v_j_0 >= v_m] (?,1) 11. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,0,v_m,v_n) [v_j_0 >= v_m && -1 + v_m >= v_j_0] (?,1) 12. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,0,v_m,v_n) [v_j_0 >= v_m && v_j_0 >= v_m] (?,1) 13. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_stop(v_i_0,v_j_0,v_m,v_n) True (?,1) Signature: {(eval_speedpldi3_0,4) ;(eval_speedpldi3_1,4) ;(eval_speedpldi3_2,4) ;(eval_speedpldi3_bb0_in,4) ;(eval_speedpldi3_bb1_in,4) ;(eval_speedpldi3_bb2_in,4) ;(eval_speedpldi3_bb3_in,4) ;(eval_speedpldi3_start,4) ;(eval_speedpldi3_stop,4)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{13},5->{13},6->{7,8},7->{9,10,11,12},8->{13},9->{7,8},10->{7,8} ,11->{7,8},12->{7,8},13->{}] + Applied Processor: TrivialSCCs + Details: All trivial SCCs of the transition graph admit timebound 1. * Step 2: UnsatRules MAYBE + Considered Problem: Rules: 0. eval_speedpldi3_start(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) True (1,1) 1. eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) True (1,1) 2. eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) True (1,1) 3. eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) True (1,1) 4. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [0 >= v_m] (1,1) 5. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_m >= v_n] (1,1) 6. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(0,0,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (1,1) 7. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) [-1 + v_n >= v_i_0] (?,1) 8. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_i_0 >= v_n] (1,1) 9. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && -1 + v_m >= v_j_0] (?,1) 10. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && v_j_0 >= v_m] (?,1) 11. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,0,v_m,v_n) [v_j_0 >= v_m && -1 + v_m >= v_j_0] (?,1) 12. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,0,v_m,v_n) [v_j_0 >= v_m && v_j_0 >= v_m] (?,1) 13. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_stop(v_i_0,v_j_0,v_m,v_n) True (1,1) Signature: {(eval_speedpldi3_0,4) ;(eval_speedpldi3_1,4) ;(eval_speedpldi3_2,4) ;(eval_speedpldi3_bb0_in,4) ;(eval_speedpldi3_bb1_in,4) ;(eval_speedpldi3_bb2_in,4) ;(eval_speedpldi3_bb3_in,4) ;(eval_speedpldi3_start,4) ;(eval_speedpldi3_stop,4)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{13},5->{13},6->{7,8},7->{9,10,11,12},8->{13},9->{7,8},10->{7,8} ,11->{7,8},12->{7,8},13->{}] + Applied Processor: UnsatRules + Details: Following transitions have unsatisfiable constraints and are removed: [10,11] * Step 3: UnsatPaths MAYBE + Considered Problem: Rules: 0. eval_speedpldi3_start(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) True (1,1) 1. eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) True (1,1) 2. eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) True (1,1) 3. eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) True (1,1) 4. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [0 >= v_m] (1,1) 5. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_m >= v_n] (1,1) 6. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(0,0,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (1,1) 7. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) [-1 + v_n >= v_i_0] (?,1) 8. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_i_0 >= v_n] (1,1) 9. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && -1 + v_m >= v_j_0] (?,1) 12. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,0,v_m,v_n) [v_j_0 >= v_m && v_j_0 >= v_m] (?,1) 13. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_stop(v_i_0,v_j_0,v_m,v_n) True (1,1) Signature: {(eval_speedpldi3_0,4) ;(eval_speedpldi3_1,4) ;(eval_speedpldi3_2,4) ;(eval_speedpldi3_bb0_in,4) ;(eval_speedpldi3_bb1_in,4) ;(eval_speedpldi3_bb2_in,4) ;(eval_speedpldi3_bb3_in,4) ;(eval_speedpldi3_start,4) ;(eval_speedpldi3_stop,4)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{13},5->{13},6->{7,8},7->{9,12},8->{13},9->{7,8},12->{7,8},13->{}] + Applied Processor: UnsatPaths + Details: We remove following edges from the transition graph: [(6,8)] * Step 4: AddSinks MAYBE + Considered Problem: Rules: 0. eval_speedpldi3_start(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) True (1,1) 1. eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) True (1,1) 2. eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) True (1,1) 3. eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) True (1,1) 4. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [0 >= v_m] (1,1) 5. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_m >= v_n] (1,1) 6. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(0,0,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (1,1) 7. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) [-1 + v_n >= v_i_0] (?,1) 8. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_i_0 >= v_n] (1,1) 9. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && -1 + v_m >= v_j_0] (?,1) 12. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,0,v_m,v_n) [v_j_0 >= v_m && v_j_0 >= v_m] (?,1) 13. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_stop(v_i_0,v_j_0,v_m,v_n) True (1,1) Signature: {(eval_speedpldi3_0,4) ;(eval_speedpldi3_1,4) ;(eval_speedpldi3_2,4) ;(eval_speedpldi3_bb0_in,4) ;(eval_speedpldi3_bb1_in,4) ;(eval_speedpldi3_bb2_in,4) ;(eval_speedpldi3_bb3_in,4) ;(eval_speedpldi3_start,4) ;(eval_speedpldi3_stop,4)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{13},5->{13},6->{7},7->{9,12},8->{13},9->{7,8},12->{7,8},13->{}] + Applied Processor: AddSinks + Details: () * Step 5: UnsatPaths MAYBE + Considered Problem: Rules: 0. eval_speedpldi3_start(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) True (1,1) 1. eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) True (?,1) 2. eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) True (?,1) 3. eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) True (?,1) 4. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [0 >= v_m] (?,1) 5. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_m >= v_n] (?,1) 6. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(0,0,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (?,1) 7. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) [-1 + v_n >= v_i_0] (?,1) 8. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_i_0 >= v_n] (?,1) 9. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && -1 + v_m >= v_j_0] (?,1) 12. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,0,v_m,v_n) [v_j_0 >= v_m && v_j_0 >= v_m] (?,1) 13. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_stop(v_i_0,v_j_0,v_m,v_n) True (?,1) 14. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> exitus616(v_i_0,v_j_0,v_m,v_n) True (?,1) Signature: {(eval_speedpldi3_0,4) ;(eval_speedpldi3_1,4) ;(eval_speedpldi3_2,4) ;(eval_speedpldi3_bb0_in,4) ;(eval_speedpldi3_bb1_in,4) ;(eval_speedpldi3_bb2_in,4) ;(eval_speedpldi3_bb3_in,4) ;(eval_speedpldi3_start,4) ;(eval_speedpldi3_stop,4) ;(exitus616,4)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{13,14},5->{13,14},6->{7,8},7->{9,12},8->{13,14},9->{7,8},12->{7,8} ,13->{},14->{}] + Applied Processor: UnsatPaths + Details: We remove following edges from the transition graph: [(6,8)] * Step 6: Failure MAYBE + Considered Problem: Rules: 0. eval_speedpldi3_start(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) True (1,1) 1. eval_speedpldi3_bb0_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) True (?,1) 2. eval_speedpldi3_0(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) True (?,1) 3. eval_speedpldi3_1(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) True (?,1) 4. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [0 >= v_m] (?,1) 5. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_m >= v_n] (?,1) 6. eval_speedpldi3_2(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(0,0,v_m,v_n) [-1 + v_m >= 0 && -1 + v_n >= v_m] (?,1) 7. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) [-1 + v_n >= v_i_0] (?,1) 8. eval_speedpldi3_bb1_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) [v_i_0 >= v_n] (?,1) 9. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(v_i_0,1 + v_j_0,v_m,v_n) [-1 + v_m >= v_j_0 && -1 + v_m >= v_j_0] (?,1) 12. eval_speedpldi3_bb2_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_bb1_in(1 + v_i_0,0,v_m,v_n) [v_j_0 >= v_m && v_j_0 >= v_m] (?,1) 13. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> eval_speedpldi3_stop(v_i_0,v_j_0,v_m,v_n) True (?,1) 14. eval_speedpldi3_bb3_in(v_i_0,v_j_0,v_m,v_n) -> exitus616(v_i_0,v_j_0,v_m,v_n) True (?,1) Signature: {(eval_speedpldi3_0,4) ;(eval_speedpldi3_1,4) ;(eval_speedpldi3_2,4) ;(eval_speedpldi3_bb0_in,4) ;(eval_speedpldi3_bb1_in,4) ;(eval_speedpldi3_bb2_in,4) ;(eval_speedpldi3_bb3_in,4) ;(eval_speedpldi3_start,4) ;(eval_speedpldi3_stop,4) ;(exitus616,4)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5,6},4->{13,14},5->{13,14},6->{7},7->{9,12},8->{13,14},9->{7,8},12->{7,8} ,13->{},14->{}] + Applied Processor: LooptreeTransformer + Details: We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,12,13,14] | `- p:[7,9,12] c: [] MAYBE