MAYBE * Step 1: TrivialSCCs MAYBE + Considered Problem: Rules: 0. eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True (1,1) 1. eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True (?,1) 2. eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True (?,1) 3. eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True (?,1) 4. eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True (?,1) 5. eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True (?,1) 6. eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True (?,1) 7. eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True (?,1) 8. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [-1 + v_n >= v__0] (?,1) 9. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__0 >= v_n] (?,1) 10. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [-1 + v__01 >= v__0 && -1 + v__01 >= v__0] (?,1) 11. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) [-1 + v__01 >= v__0 && v__0 >= v__01] (?,1) 12. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,1 + v__01,v_n,v_x,v_z) [v__0 >= v__01 && -1 + v__01 >= v__0] (?,1) 13. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__0 >= v__01 && v__0 >= v__01] (?,1) 14. eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) True (?,1) Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,11,12,13},9->{14},10->{8,9},11->{8,9} ,12->{8,9},13->{8,9},14->{}] + Applied Processor: TrivialSCCs + Details: All trivial SCCs of the transition graph admit timebound 1. * Step 2: UnsatRules MAYBE + Considered Problem: Rules: 0. eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True (1,1) 1. eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True (1,1) 2. eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True (1,1) 3. eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True (1,1) 4. eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True (1,1) 5. eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True (1,1) 6. eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True (1,1) 7. eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True (1,1) 8. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [-1 + v_n >= v__0] (?,1) 9. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__0 >= v_n] (1,1) 10. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [-1 + v__01 >= v__0 && -1 + v__01 >= v__0] (?,1) 11. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) [-1 + v__01 >= v__0 && v__0 >= v__01] (?,1) 12. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,1 + v__01,v_n,v_x,v_z) [v__0 >= v__01 && -1 + v__01 >= v__0] (?,1) 13. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__0 >= v__01 && v__0 >= v__01] (?,1) 14. eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) True (1,1) Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,11,12,13},9->{14},10->{8,9},11->{8,9} ,12->{8,9},13->{8,9},14->{}] + Applied Processor: UnsatRules + Details: Following transitions have unsatisfiable constraints and are removed: [11,12] * Step 3: AddSinks MAYBE + Considered Problem: Rules: 0. eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True (1,1) 1. eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True (1,1) 2. eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True (1,1) 3. eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True (1,1) 4. eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True (1,1) 5. eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True (1,1) 6. eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True (1,1) 7. eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True (1,1) 8. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [-1 + v_n >= v__0] (?,1) 9. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__0 >= v_n] (1,1) 10. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [-1 + v__01 >= v__0 && -1 + v__01 >= v__0] (?,1) 13. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__0 >= v__01 && v__0 >= v__01] (?,1) 14. eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) True (1,1) Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,13},9->{14},10->{8,9},13->{8,9},14->{}] + Applied Processor: AddSinks + Details: () * Step 4: Failure MAYBE + Considered Problem: Rules: 0. eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True (1,1) 1. eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True (?,1) 2. eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True (?,1) 3. eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True (?,1) 4. eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True (?,1) 5. eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True (?,1) 6. eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True (?,1) 7. eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True (?,1) 8. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [-1 + v_n >= v__0] (?,1) 9. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__0 >= v_n] (?,1) 10. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [-1 + v__01 >= v__0 && -1 + v__01 >= v__0] (?,1) 13. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__0 >= v__01 && v__0 >= v__01] (?,1) 14. eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) True (?,1) 15. eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> exitus616(v__0,v__01,v_n,v_x,v_z) True (?,1) Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5) ;(exitus616,5)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,13},9->{14,15},10->{8,9},13->{8,9} ,14->{},15->{}] + Applied Processor: LooptreeTransformer + Details: We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,13,14,15] | `- p:[8,10,13] c: [] MAYBE