YES(?,POLY) * Step 1: TrivialSCCs WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 1. eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 2. eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 3. eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 4. eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 5. eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 6. eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 7. eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 8. eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x,v_y) True (?,1) 9. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) [-1 + v_n >= v__0] (?,1) 10. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__0 >= v_n] (?,1) 11. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] (?,1) 12. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && v__01 >= v_m] (?,1) 13. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && -1 + v_m >= v__01] (?,1) 14. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && v__01 >= v_m] (?,1) 15. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,12,13,14},10->{15},11->{9,10} ,12->{9,10},13->{9,10},14->{9,10},15->{}] + Applied Processor: TrivialSCCs + Details: All trivial SCCs of the transition graph admit timebound 1. * Step 2: UnsatRules WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 1. eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 2. eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 3. eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 4. eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 5. eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 6. eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 7. eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 8. eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x,v_y) True (1,1) 9. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) [-1 + v_n >= v__0] (?,1) 10. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__0 >= v_n] (1,1) 11. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] (?,1) 12. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && v__01 >= v_m] (?,1) 13. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && -1 + v_m >= v__01] (?,1) 14. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && v__01 >= v_m] (?,1) 15. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,12,13,14},10->{15},11->{9,10} ,12->{9,10},13->{9,10},14->{9,10},15->{}] + Applied Processor: UnsatRules + Details: Following transitions have unsatisfiable constraints and are removed: [12,13] * Step 3: AddSinks WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 1. eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 2. eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 3. eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 4. eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 5. eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 6. eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 7. eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 8. eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x,v_y) True (1,1) 9. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) [-1 + v_n >= v__0] (?,1) 10. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__0 >= v_n] (1,1) 11. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] (?,1) 14. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && v__01 >= v_m] (?,1) 15. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,14},10->{15},11->{9,10},14->{9 ,10},15->{}] + Applied Processor: AddSinks + Details: () * Step 4: LooptreeTransformer WORST_CASE(?,POLY) + Considered Problem: Rules: 0. eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 1. eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 2. eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 3. eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 4. eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 5. eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 6. eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 7. eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 8. eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x,v_y) True (?,1) 9. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) [-1 + v_n >= v__0] (?,1) 10. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__0 >= v_n] (?,1) 11. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] (?,1) 14. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && v__01 >= v_m] (?,1) 15. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 16. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> exitus616(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6) ;(exitus616,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,14},10->{15,16},11->{9,10} ,14->{9,10},15->{},16->{}] + Applied Processor: LooptreeTransformer + Details: We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,14,15,16] | `- p:[9,11,14] c: [11] | `- p:[9,14] c: [9] * Step 5: SizeAbstraction WORST_CASE(?,POLY) + Considered Problem: (Rules: 0. eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 1. eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 2. eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 3. eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 4. eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 5. eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 6. eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 7. eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 8. eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x,v_y) True (?,1) 9. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) [-1 + v_n >= v__0] (?,1) 10. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__0 >= v_n] (?,1) 11. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] (?,1) 14. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && v__01 >= v_m] (?,1) 15. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 16. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> exitus616(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6) ;(exitus616,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,14},10->{15,16},11->{9,10} ,14->{9,10},15->{},16->{}] ,We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,14,15,16] | `- p:[9,11,14] c: [11] | `- p:[9,14] c: [9]) + Applied Processor: SizeAbstraction UseCFG Minimize + Details: () * Step 6: FlowAbstraction WORST_CASE(?,POLY) + Considered Problem: Program: Domain: [v__0,v__01,v_m,v_n,v_x,v_y,0.0,0.0.0] eval_speedDis1_start ~> eval_speedDis1_bb0_in [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb0_in ~> eval_speedDis1_0 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_0 ~> eval_speedDis1_1 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_1 ~> eval_speedDis1_2 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_2 ~> eval_speedDis1_3 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_3 ~> eval_speedDis1_4 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_4 ~> eval_speedDis1_5 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_5 ~> eval_speedDis1_6 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_6 ~> eval_speedDis1_bb1_in [v__0 <= v_x, v__01 <= v_y, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb1_in ~> eval_speedDis1_bb2_in [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb1_in ~> eval_speedDis1_bb3_in [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 <= v__0, v__01 <= v__01 + v_m, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 <= K + v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb3_in ~> eval_speedDis1_stop [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb3_in ~> exitus616 [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] + Loop: [0.0 <= K + v__01 + v_m] eval_speedDis1_bb1_in ~> eval_speedDis1_bb2_in [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 <= v__0, v__01 <= v__01 + v_m, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 <= K + v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] + Loop: [0.0.0 <= 2*K + v__0 + v_n] eval_speedDis1_bb1_in ~> eval_speedDis1_bb2_in [v__0 <= v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 <= K + v__0, v__01 <= v__01, v_m <= v_m, v_n <= v_n, v_x <= v_x, v_y <= v_y] + Applied Processor: FlowAbstraction + Details: () * Step 7: LareProcessor WORST_CASE(?,POLY) + Considered Problem: Program: Domain: [tick,huge,K,v__0,v__01,v_m,v_n,v_x,v_y,0.0,0.0.0] eval_speedDis1_start ~> eval_speedDis1_bb0_in [] eval_speedDis1_bb0_in ~> eval_speedDis1_0 [] eval_speedDis1_0 ~> eval_speedDis1_1 [] eval_speedDis1_1 ~> eval_speedDis1_2 [] eval_speedDis1_2 ~> eval_speedDis1_3 [] eval_speedDis1_3 ~> eval_speedDis1_4 [] eval_speedDis1_4 ~> eval_speedDis1_5 [] eval_speedDis1_5 ~> eval_speedDis1_6 [] eval_speedDis1_6 ~> eval_speedDis1_bb1_in [v_x ~=> v__0,v_y ~=> v__01] eval_speedDis1_bb1_in ~> eval_speedDis1_bb2_in [] eval_speedDis1_bb1_in ~> eval_speedDis1_bb3_in [] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__01 ~+> v__01,v_m ~+> v__01] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 ~+> v__0,K ~+> v__0] eval_speedDis1_bb3_in ~> eval_speedDis1_stop [] eval_speedDis1_bb3_in ~> exitus616 [] + Loop: [v__01 ~+> 0.0,v_m ~+> 0.0,K ~+> 0.0] eval_speedDis1_bb1_in ~> eval_speedDis1_bb2_in [] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__01 ~+> v__01,v_m ~+> v__01] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 ~+> v__0,K ~+> v__0] + Loop: [v__0 ~+> 0.0.0,v_n ~+> 0.0.0,K ~*> 0.0.0] eval_speedDis1_bb1_in ~> eval_speedDis1_bb2_in [] eval_speedDis1_bb2_in ~> eval_speedDis1_bb1_in [v__0 ~+> v__0,K ~+> v__0] + Applied Processor: LareProcessor + Details: eval_speedDis1_start ~> eval_speedDis1_stop [v_x ~=> v__0 ,v_y ~=> v__01 ,v_m ~+> v__01 ,v_m ~+> 0.0 ,v_m ~+> tick ,v_n ~+> 0.0.0 ,v_n ~+> tick ,v_x ~+> v__0 ,v_x ~+> 0.0.0 ,v_x ~+> tick ,v_y ~+> v__01 ,v_y ~+> 0.0 ,v_y ~+> tick ,tick ~+> tick ,K ~+> v__0 ,K ~+> 0.0 ,K ~+> 0.0.0 ,K ~+> tick ,v_m ~*> v__0 ,v_m ~*> v__01 ,v_m ~*> tick ,v_n ~*> v__0 ,v_n ~*> 0.0.0 ,v_n ~*> tick ,v_x ~*> v__0 ,v_x ~*> 0.0.0 ,v_x ~*> tick ,v_y ~*> v__0 ,v_y ~*> v__01 ,v_y ~*> tick ,K ~*> v__0 ,K ~*> v__01 ,K ~*> 0.0.0 ,K ~*> tick ,v_m ~^> v__0 ,v_y ~^> v__0 ,K ~^> v__0] eval_speedDis1_start ~> exitus616 [v_x ~=> v__0 ,v_y ~=> v__01 ,v_m ~+> v__01 ,v_m ~+> 0.0 ,v_m ~+> tick ,v_n ~+> 0.0.0 ,v_n ~+> tick ,v_x ~+> v__0 ,v_x ~+> 0.0.0 ,v_x ~+> tick ,v_y ~+> v__01 ,v_y ~+> 0.0 ,v_y ~+> tick ,tick ~+> tick ,K ~+> v__0 ,K ~+> 0.0 ,K ~+> 0.0.0 ,K ~+> tick ,v_m ~*> v__0 ,v_m ~*> v__01 ,v_m ~*> tick ,v_n ~*> v__0 ,v_n ~*> 0.0.0 ,v_n ~*> tick ,v_x ~*> v__0 ,v_x ~*> 0.0.0 ,v_x ~*> tick ,v_y ~*> v__0 ,v_y ~*> v__01 ,v_y ~*> tick ,K ~*> v__0 ,K ~*> v__01 ,K ~*> 0.0.0 ,K ~*> tick ,v_m ~^> v__0 ,v_y ~^> v__0 ,K ~^> v__0] + eval_speedDis1_bb1_in> [v__0 ~+> v__0 ,v__0 ~+> 0.0.0 ,v__0 ~+> tick ,v__01 ~+> v__01 ,v__01 ~+> 0.0 ,v__01 ~+> tick ,v_m ~+> v__01 ,v_m ~+> 0.0 ,v_m ~+> tick ,v_n ~+> 0.0.0 ,v_n ~+> tick ,tick ~+> tick ,K ~+> v__0 ,K ~+> 0.0 ,K ~+> 0.0.0 ,K ~+> tick ,v__0 ~*> v__0 ,v__0 ~*> 0.0.0 ,v__0 ~*> tick ,v__01 ~*> v__0 ,v__01 ~*> v__01 ,v__01 ~*> tick ,v_m ~*> v__0 ,v_m ~*> v__01 ,v_m ~*> tick ,v_n ~*> v__0 ,v_n ~*> 0.0.0 ,v_n ~*> tick ,K ~*> v__0 ,K ~*> v__01 ,K ~*> 0.0.0 ,K ~*> tick ,v__01 ~^> v__0 ,v_m ~^> v__0 ,K ~^> v__0] + eval_speedDis1_bb2_in> [v__0 ~+> v__0 ,v__0 ~+> 0.0.0 ,v__0 ~+> tick ,v_n ~+> 0.0.0 ,v_n ~+> tick ,tick ~+> tick ,K ~+> v__0 ,v__0 ~*> v__0 ,v_n ~*> v__0 ,K ~*> v__0 ,K ~*> 0.0.0 ,K ~*> tick] eval_speedDis1_bb1_in> [v__0 ~+> v__0 ,v__0 ~+> 0.0.0 ,v__0 ~+> tick ,v_n ~+> 0.0.0 ,v_n ~+> tick ,tick ~+> tick ,K ~+> v__0 ,v__0 ~*> v__0 ,v_n ~*> v__0 ,K ~*> v__0 ,K ~*> 0.0.0 ,K ~*> tick] YES(?,POLY)