MAYBE * Step 1: TrivialSCCs MAYBE + Considered Problem: Rules: 0. eval_rsd_start(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 1. eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 2. eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 3. eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 4. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_r >= 0] (?,1) 5. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 >= v_r] (?,1) 6. eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_4(2*v_r,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 7. eval_rsd_4(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 8. eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_6(v_1,2*v_r,v_4,v_da_0,v_db_0,v_r) True (?,1) 9. eval_rsd_6(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 10. eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 11. eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 12. eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 13. eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 14. eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 15. eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,v_1,v_2,v_r) True (?,1) 16. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_da_0 >= v_r] (?,1) 17. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 + v_r >= v_da_0] (?,1) 18. eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 19. eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_14(v_1,v_2,nondef_0,v_da_0,v_db_0,v_r) True (?,1) 20. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_da_0,v_db_0,v_r) [-1 + v_4 >= 0 && -1 + v_4 >= 0] (?,1) 21. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_db_0,v_db_0,v_r) [-1 + v_4 >= 0 && 0 >= v_4] (?,1) 22. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_da_0,v_da_0,v_r) [0 >= v_4 && -1 + v_4 >= 0] (?,1) 23. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_db_0,v_da_0,v_r) [0 >= v_4 && 0 >= v_4] (?,1) 24. eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_stop(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) Signature: {(eval_rsd_0,6) ;(eval_rsd_1,6) ;(eval_rsd_10,6) ;(eval_rsd_11,6) ;(eval_rsd_12,6) ;(eval_rsd_13,6) ;(eval_rsd_14,6) ;(eval_rsd_2,6) ;(eval_rsd_4,6) ;(eval_rsd_5,6) ;(eval_rsd_6,6) ;(eval_rsd_7,6) ;(eval_rsd_8,6) ;(eval_rsd_9,6) ;(eval_rsd_bb0_in,6) ;(eval_rsd_bb1_in,6) ;(eval_rsd_bb2_in,6) ;(eval_rsd_bb3_in,6) ;(eval_rsd_bb4_in,6) ;(eval_rsd_start,6) ;(eval_rsd_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5},4->{6},5->{24},6->{7},7->{8},8->{9},9->{10},10->{11},11->{12},12->{13} ,13->{14},14->{15},15->{16,17},16->{18},17->{24},18->{19},19->{20,21,22,23},20->{16,17},21->{16,17},22->{16 ,17},23->{16,17},24->{}] + Applied Processor: TrivialSCCs + Details: All trivial SCCs of the transition graph admit timebound 1. * Step 2: UnsatRules MAYBE + Considered Problem: Rules: 0. eval_rsd_start(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 1. eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 2. eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 3. eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 4. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_r >= 0] (1,1) 5. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 >= v_r] (1,1) 6. eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_4(2*v_r,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 7. eval_rsd_4(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 8. eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_6(v_1,2*v_r,v_4,v_da_0,v_db_0,v_r) True (1,1) 9. eval_rsd_6(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 10. eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 11. eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 12. eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 13. eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 14. eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 15. eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,v_1,v_2,v_r) True (1,1) 16. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_da_0 >= v_r] (?,1) 17. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 + v_r >= v_da_0] (1,1) 18. eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 19. eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_14(v_1,v_2,nondef_0,v_da_0,v_db_0,v_r) True (?,1) 20. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_da_0,v_db_0,v_r) [-1 + v_4 >= 0 && -1 + v_4 >= 0] (?,1) 21. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_db_0,v_db_0,v_r) [-1 + v_4 >= 0 && 0 >= v_4] (?,1) 22. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_da_0,v_da_0,v_r) [0 >= v_4 && -1 + v_4 >= 0] (?,1) 23. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_db_0,v_da_0,v_r) [0 >= v_4 && 0 >= v_4] (?,1) 24. eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_stop(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) Signature: {(eval_rsd_0,6) ;(eval_rsd_1,6) ;(eval_rsd_10,6) ;(eval_rsd_11,6) ;(eval_rsd_12,6) ;(eval_rsd_13,6) ;(eval_rsd_14,6) ;(eval_rsd_2,6) ;(eval_rsd_4,6) ;(eval_rsd_5,6) ;(eval_rsd_6,6) ;(eval_rsd_7,6) ;(eval_rsd_8,6) ;(eval_rsd_9,6) ;(eval_rsd_bb0_in,6) ;(eval_rsd_bb1_in,6) ;(eval_rsd_bb2_in,6) ;(eval_rsd_bb3_in,6) ;(eval_rsd_bb4_in,6) ;(eval_rsd_start,6) ;(eval_rsd_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5},4->{6},5->{24},6->{7},7->{8},8->{9},9->{10},10->{11},11->{12},12->{13} ,13->{14},14->{15},15->{16,17},16->{18},17->{24},18->{19},19->{20,21,22,23},20->{16,17},21->{16,17},22->{16 ,17},23->{16,17},24->{}] + Applied Processor: UnsatRules + Details: Following transitions have unsatisfiable constraints and are removed: [21,22] * Step 3: AddSinks MAYBE + Considered Problem: Rules: 0. eval_rsd_start(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 1. eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 2. eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 3. eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 4. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_r >= 0] (1,1) 5. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 >= v_r] (1,1) 6. eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_4(2*v_r,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 7. eval_rsd_4(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 8. eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_6(v_1,2*v_r,v_4,v_da_0,v_db_0,v_r) True (1,1) 9. eval_rsd_6(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 10. eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 11. eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 12. eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 13. eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 14. eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 15. eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,v_1,v_2,v_r) True (1,1) 16. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_da_0 >= v_r] (?,1) 17. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 + v_r >= v_da_0] (1,1) 18. eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 19. eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_14(v_1,v_2,nondef_0,v_da_0,v_db_0,v_r) True (?,1) 20. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_da_0,v_db_0,v_r) [-1 + v_4 >= 0 && -1 + v_4 >= 0] (?,1) 23. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_db_0,v_da_0,v_r) [0 >= v_4 && 0 >= v_4] (?,1) 24. eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_stop(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) Signature: {(eval_rsd_0,6) ;(eval_rsd_1,6) ;(eval_rsd_10,6) ;(eval_rsd_11,6) ;(eval_rsd_12,6) ;(eval_rsd_13,6) ;(eval_rsd_14,6) ;(eval_rsd_2,6) ;(eval_rsd_4,6) ;(eval_rsd_5,6) ;(eval_rsd_6,6) ;(eval_rsd_7,6) ;(eval_rsd_8,6) ;(eval_rsd_9,6) ;(eval_rsd_bb0_in,6) ;(eval_rsd_bb1_in,6) ;(eval_rsd_bb2_in,6) ;(eval_rsd_bb3_in,6) ;(eval_rsd_bb4_in,6) ;(eval_rsd_start,6) ;(eval_rsd_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5},4->{6},5->{24},6->{7},7->{8},8->{9},9->{10},10->{11},11->{12},12->{13} ,13->{14},14->{15},15->{16,17},16->{18},17->{24},18->{19},19->{20,23},20->{16,17},23->{16,17},24->{}] + Applied Processor: AddSinks + Details: () * Step 4: Failure MAYBE + Considered Problem: Rules: 0. eval_rsd_start(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (1,1) 1. eval_rsd_bb0_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 2. eval_rsd_0(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 3. eval_rsd_1(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 4. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_r >= 0] (?,1) 5. eval_rsd_2(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 >= v_r] (?,1) 6. eval_rsd_bb1_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_4(2*v_r,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 7. eval_rsd_4(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 8. eval_rsd_5(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_6(v_1,2*v_r,v_4,v_da_0,v_db_0,v_r) True (?,1) 9. eval_rsd_6(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 10. eval_rsd_7(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 11. eval_rsd_8(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 12. eval_rsd_9(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 13. eval_rsd_10(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 14. eval_rsd_11(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 15. eval_rsd_12(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,v_1,v_2,v_r) True (?,1) 16. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [v_da_0 >= v_r] (?,1) 17. eval_rsd_bb2_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) [-1 + v_r >= v_da_0] (?,1) 18. eval_rsd_bb3_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 19. eval_rsd_13(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_14(v_1,v_2,nondef_0,v_da_0,v_db_0,v_r) True (?,1) 20. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_da_0,v_db_0,v_r) [-1 + v_4 >= 0 && -1 + v_4 >= 0] (?,1) 23. eval_rsd_14(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_bb2_in(v_1,v_2,v_4,-1 + v_db_0,v_da_0,v_r) [0 >= v_4 && 0 >= v_4] (?,1) 24. eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> eval_rsd_stop(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) 25. eval_rsd_bb4_in(v_1,v_2,v_4,v_da_0,v_db_0,v_r) -> exitus616(v_1,v_2,v_4,v_da_0,v_db_0,v_r) True (?,1) Signature: {(eval_rsd_0,6) ;(eval_rsd_1,6) ;(eval_rsd_10,6) ;(eval_rsd_11,6) ;(eval_rsd_12,6) ;(eval_rsd_13,6) ;(eval_rsd_14,6) ;(eval_rsd_2,6) ;(eval_rsd_4,6) ;(eval_rsd_5,6) ;(eval_rsd_6,6) ;(eval_rsd_7,6) ;(eval_rsd_8,6) ;(eval_rsd_9,6) ;(eval_rsd_bb0_in,6) ;(eval_rsd_bb1_in,6) ;(eval_rsd_bb2_in,6) ;(eval_rsd_bb3_in,6) ;(eval_rsd_bb4_in,6) ;(eval_rsd_start,6) ;(eval_rsd_stop,6) ;(exitus616,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4,5},4->{6},5->{24,25},6->{7},7->{8},8->{9},9->{10},10->{11},11->{12},12->{13} ,13->{14},14->{15},15->{16,17},16->{18},17->{24,25},18->{19},19->{20,23},20->{16,17},23->{16,17},24->{} ,25->{}] + Applied Processor: LooptreeTransformer + Details: We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,23,24,25] | `- p:[16,20,19,18,23] c: [] MAYBE