YES(?,O(n^1)) * Step 1: UnsatPaths WORST_CASE(?,O(n^1)) + Considered Problem: Rules: 0. eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True (1,1) 1. eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True (?,1) 2. eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True (?,1) 3. eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True (?,1) 4. eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True (?,1) 5. eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True (?,1) 6. eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True (?,1) 7. eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True (?,1) 8. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && -1 + v_n >= v__0] (?,1) 9. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 >= v_n] (?,1) 10. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 (?,1) && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && -1 + v__01 >= v__0] 11. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 (?,1) && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && v__0 >= v__01] 12. eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 + -1*v_n >= 0] (?,1) Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,11},9->{12},10->{8,9},11->{8,9},12->{}] + Applied Processor: UnsatPaths + Details: We remove following edges from the transition graph: [(11,9)] * Step 2: FromIts WORST_CASE(?,O(n^1)) + Considered Problem: Rules: 0. eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True (1,1) 1. eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True (?,1) 2. eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True (?,1) 3. eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True (?,1) 4. eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True (?,1) 5. eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True (?,1) 6. eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True (?,1) 7. eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True (?,1) 8. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && -1 + v_n >= v__0] (?,1) 9. eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 >= v_n] (?,1) 10. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 (?,1) && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && -1 + v__01 >= v__0] 11. eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 (?,1) && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && v__0 >= v__01] 12. eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 + -1*v_n >= 0] (?,1) Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,11},9->{12},10->{8,9},11->{8},12->{}] + Applied Processor: FromIts + Details: () * Step 3: AddSinks WORST_CASE(?,O(n^1)) + Considered Problem: Rules: eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && -1 + v_n >= v__0] eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 >= v_n] eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && -1 + v__01 >= v__0] eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && v__0 >= v__01] eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 + -1*v_n >= 0] Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5)} Rule Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,11},9->{12},10->{8,9},11->{8},12->{}] + Applied Processor: AddSinks + Details: () * Step 4: Decompose WORST_CASE(?,O(n^1)) + Considered Problem: Rules: eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && -1 + v_n >= v__0] eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 >= v_n] eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && -1 + v__01 >= v__0] eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && v__0 >= v__01] eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 + -1*v_n >= 0] eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) -> exitus616(v__0,v__01,v_n,v_x,v_z) True Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5) ;(exitus616,5)} Rule Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,11},9->{12},10->{8,9},11->{8},12->{13}] + Applied Processor: Decompose Greedy + Details: We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,12,13] | `- p:[8,10,11] c: [8,10,11] * Step 5: AbstractSize WORST_CASE(?,O(n^1)) + Considered Problem: (Rules: eval_speedDis2_start(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_bb0_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_0(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_1(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_2(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_3(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_4(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) True eval_speedDis2_5(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v_x,v_z,v_n,v_x,v_z) True eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && -1 + v_n >= v__0] eval_speedDis2_bb1_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 >= v_n] eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(1 + v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && -1 + v__01 >= v__0] eval_speedDis2_bb2_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_bb1_in(v__0,1 + v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && -1 + v_n + -1*v_x >= 0 && v__0 + -1*v_x >= 0 && -1 + -1*v__0 + v_n >= 0 && v__0 >= v__01] eval_speedDis2_bb3_in(v__0,v__01,v_n,v_x,v_z) -> eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) [v__01 + -1*v_z >= 0 && v__0 + -1*v_x >= 0 && v__0 + -1*v_n >= 0] eval_speedDis2_stop(v__0,v__01,v_n,v_x,v_z) -> exitus616(v__0,v__01,v_n,v_x,v_z) True Signature: {(eval_speedDis2_0,5) ;(eval_speedDis2_1,5) ;(eval_speedDis2_2,5) ;(eval_speedDis2_3,5) ;(eval_speedDis2_4,5) ;(eval_speedDis2_5,5) ;(eval_speedDis2_bb0_in,5) ;(eval_speedDis2_bb1_in,5) ;(eval_speedDis2_bb2_in,5) ;(eval_speedDis2_bb3_in,5) ;(eval_speedDis2_start,5) ;(eval_speedDis2_stop,5) ;(exitus616,5)} Rule Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8,9},8->{10,11},9->{12},10->{8,9},11->{8},12->{13}] ,We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,12,13] | `- p:[8,10,11] c: [8,10,11]) + Applied Processor: AbstractSize Minimize + Details: () * Step 6: AbstractFlow WORST_CASE(?,O(n^1)) + Considered Problem: Program: Domain: [v__0,v__01,v_n,v_x,v_z,0.0] eval_speedDis2_start ~> eval_speedDis2_bb0_in [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb0_in ~> eval_speedDis2_0 [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_0 ~> eval_speedDis2_1 [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_1 ~> eval_speedDis2_2 [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_2 ~> eval_speedDis2_3 [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_3 ~> eval_speedDis2_4 [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_4 ~> eval_speedDis2_5 [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_5 ~> eval_speedDis2_bb1_in [v__0 <= v_x, v__01 <= v_z, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb1_in ~> eval_speedDis2_bb2_in [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb1_in ~> eval_speedDis2_bb3_in [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__0 <= v__0 + v_n, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__0 <= v__0, v__01 <= v__01 + v_n, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb3_in ~> eval_speedDis2_stop [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_stop ~> exitus616 [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] + Loop: [0.0 <= K + v__0 + v__01 + v_n] eval_speedDis2_bb1_in ~> eval_speedDis2_bb2_in [v__0 <= v__0, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__0 <= v__0 + v_n, v__01 <= v__01, v_n <= v_n, v_x <= v_x, v_z <= v_z] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__0 <= v__0, v__01 <= v__01 + v_n, v_n <= v_n, v_x <= v_x, v_z <= v_z] + Applied Processor: AbstractFlow + Details: () * Step 7: Lare WORST_CASE(?,O(n^1)) + Considered Problem: Program: Domain: [tick,huge,K,v__0,v__01,v_n,v_x,v_z,0.0] eval_speedDis2_start ~> eval_speedDis2_bb0_in [] eval_speedDis2_bb0_in ~> eval_speedDis2_0 [] eval_speedDis2_0 ~> eval_speedDis2_1 [] eval_speedDis2_1 ~> eval_speedDis2_2 [] eval_speedDis2_2 ~> eval_speedDis2_3 [] eval_speedDis2_3 ~> eval_speedDis2_4 [] eval_speedDis2_4 ~> eval_speedDis2_5 [] eval_speedDis2_5 ~> eval_speedDis2_bb1_in [v_x ~=> v__0,v_z ~=> v__01] eval_speedDis2_bb1_in ~> eval_speedDis2_bb2_in [] eval_speedDis2_bb1_in ~> eval_speedDis2_bb3_in [] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__0 ~+> v__0,v_n ~+> v__0] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__01 ~+> v__01,v_n ~+> v__01] eval_speedDis2_bb3_in ~> eval_speedDis2_stop [] eval_speedDis2_stop ~> exitus616 [] + Loop: [v__0 ~+> 0.0,v__01 ~+> 0.0,v_n ~+> 0.0,K ~+> 0.0] eval_speedDis2_bb1_in ~> eval_speedDis2_bb2_in [] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__0 ~+> v__0,v_n ~+> v__0] eval_speedDis2_bb2_in ~> eval_speedDis2_bb1_in [v__01 ~+> v__01,v_n ~+> v__01] + Applied Processor: Lare + Details: eval_speedDis2_start ~> exitus616 [v_x ~=> v__0 ,v_z ~=> v__01 ,v_n ~+> v__0 ,v_n ~+> v__01 ,v_n ~+> 0.0 ,v_n ~+> tick ,v_x ~+> v__0 ,v_x ~+> 0.0 ,v_x ~+> tick ,v_z ~+> v__01 ,v_z ~+> 0.0 ,v_z ~+> tick ,tick ~+> tick ,K ~+> 0.0 ,K ~+> tick ,v_n ~*> v__0 ,v_n ~*> v__01 ,v_x ~*> v__0 ,v_x ~*> v__01 ,v_z ~*> v__0 ,v_z ~*> v__01 ,K ~*> v__0 ,K ~*> v__01] + eval_speedDis2_bb1_in> [v__0 ~+> v__0 ,v__0 ~+> 0.0 ,v__0 ~+> tick ,v__01 ~+> v__01 ,v__01 ~+> 0.0 ,v__01 ~+> tick ,v_n ~+> v__0 ,v_n ~+> v__01 ,v_n ~+> 0.0 ,v_n ~+> tick ,tick ~+> tick ,K ~+> 0.0 ,K ~+> tick ,v__0 ~*> v__0 ,v__0 ~*> v__01 ,v__01 ~*> v__0 ,v__01 ~*> v__01 ,v_n ~*> v__0 ,v_n ~*> v__01 ,K ~*> v__0 ,K ~*> v__01] YES(?,O(n^1))