YES * Step 1: UnsatRules YES + Considered Problem: Rules: 0. eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 1. eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 2. eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 3. eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 4. eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 5. eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 6. eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 7. eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 8. eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x,v_y) True (?,1) 9. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) [-1 + v_n >= v__0] (?,1) 10. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__0 >= v_n] (?,1) 11. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] (?,1) 12. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && v__01 >= v_m] (?,1) 13. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && -1 + v_m >= v__01] (?,1) 14. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && v__01 >= v_m] (?,1) 15. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,12,13,14},10->{15},11->{9,10} ,12->{9,10},13->{9,10},14->{9,10},15->{}] + Applied Processor: UnsatRules + Details: Following transitions have unsatisfiable constraints and are removed: [12,13] * Step 2: FromIts YES + Considered Problem: Rules: 0. eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) True (1,1) 1. eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 2. eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 3. eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 4. eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 5. eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 6. eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 7. eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) 8. eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x,v_y) True (?,1) 9. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) [-1 + v_n >= v__0] (?,1) 10. eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) [v__0 >= v_n] (?,1) 11. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] (?,1) 14. eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x,v_y) [v__01 >= v_m && v__01 >= v_m] (?,1) 15. eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x,v_y) True (?,1) Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6)} Flow Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,14},10->{15},11->{9,10},14->{9 ,10},15->{}] + Applied Processor: FromIts + Details: () * Step 3: Decompose YES + Considered Problem: Rules: eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x ,v_y) True eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x ,v_y) [-1 + v_n >= v__0] eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x ,v_y) [v__0 >= v_n] eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x ,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x ,v_y) [v__01 >= v_m && v__01 >= v_m] eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x ,v_y) True Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6)} Rule Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,14},10->{15},11->{9,10},14->{9 ,10},15->{}] + Applied Processor: Decompose NoGreedy + Details: We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,14,15] | `- p:[9,11,14] c: [11] | `- p:[9,14] c: [9,14] * Step 4: CloseWith YES + Considered Problem: (Rules: eval_speedDis1_start(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_bb0_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_0(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_1(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_2(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_3(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_4(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_5(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x ,v_y) True eval_speedDis1_6(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v_x,v_y,v_m,v_n,v_x ,v_y) True eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x ,v_y) [-1 + v_n >= v__0] eval_speedDis1_bb1_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x ,v_y) [v__0 >= v_n] eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(v__0,1 + v__01,v_m,v_n,v_x ,v_y) [-1 + v_m >= v__01 && -1 + v_m >= v__01] eval_speedDis1_bb2_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_bb1_in(1 + v__0,v__01,v_m,v_n,v_x ,v_y) [v__01 >= v_m && v__01 >= v_m] eval_speedDis1_bb3_in(v__0,v__01,v_m,v_n,v_x,v_y) -> eval_speedDis1_stop(v__0,v__01,v_m,v_n,v_x ,v_y) True Signature: {(eval_speedDis1_0,6) ;(eval_speedDis1_1,6) ;(eval_speedDis1_2,6) ;(eval_speedDis1_3,6) ;(eval_speedDis1_4,6) ;(eval_speedDis1_5,6) ;(eval_speedDis1_6,6) ;(eval_speedDis1_bb0_in,6) ;(eval_speedDis1_bb1_in,6) ;(eval_speedDis1_bb2_in,6) ;(eval_speedDis1_bb3_in,6) ;(eval_speedDis1_start,6) ;(eval_speedDis1_stop,6)} Rule Graph: [0->{1},1->{2},2->{3},3->{4},4->{5},5->{6},6->{7},7->{8},8->{9,10},9->{11,14},10->{15},11->{9,10},14->{9 ,10},15->{}] ,We construct a looptree: P: [0,1,2,3,4,5,6,7,8,9,10,11,14,15] | `- p:[9,11,14] c: [11] | `- p:[9,14] c: [9,14]) + Applied Processor: CloseWith True + Details: () YES